Overview
The Reality Labs Custom Silicon Program Management team at Meta is pioneering breakthrough work in AI, computer vision, machine learning, mixed reality, graphics, displays, sensors, and innovative human interface technologies. Our chips will power wearables and AR devices that seamlessly blend the real and virtual worlds. To achieve these ambitious goals, we focus on the entire technology stack—from transistor-level design, through architecture, firmware, and algorithms.
We are seeking an experienced Silicon Validation Technical Program Manager (TPM) to drive execution of post-silicon validation for Meta’s next-generation custom silicon programs powering AR/VR devices, and next-gen consumer products. You will lead XFN execution across silicon architecture, design, firmware, software, system integration teams. Your primary responsibility is to ensure that Meta’s custom silicon delivers the required performance, power, reliability, and functional correctness through rigorous post-silicon validation. You will collaborate with cross-functional teams and experience the full vertical integration of next-generation products. This position leverages your technical expertise and program management skills in a multi-functional leadership role, offering exposure to cutting-edge technologies from concept to mass production.
Responsibilities
Drive end-to-end planning and execution of post-silicon validation across Meta’s custom SoCs, accelerators, and AMS chips.
Develop and maintain integrated schedules spanning silicon bring-up, validation coverage, firmware enablement, driver readiness, tooling, and system-level test execution.
Lead cross-functional (XFN) communication, ensuring alignment across architecture, silicon design, validation, firmware, software, platform teams, product, and operations.
Run weekly XFN execution forums, issue triage sessions, and exec-level status reviews.
Understand Meta’s custom silicon architecture, IP interactions, and platform requirements sufficiently to identify validation gaps, dependencies, and risk areas.
Partner with validation teams to define test plans, KPIs, pass criteria, and coverage goals for functional, performance, system, power, thermal, and reliability testing.
Ensure bring-up activities—including boot, power sequencing, security provisioning, interface enablement, and performance characterization—are tracked and unblocked.
Drive debug coordination across silicon, firmware, and software teams; ensure issues are owned, root-caused, and driven to closure.
Ensure availability of engineering samples, validation boards, fixtures, firmware drops, and debug tools to support execution.
Partner with lab operations, automation, and tooling teams to ensure Meta’s test infrastructure (automation pipelines, dashboards, data systems) scales with program needs.
Oversee execution readiness for key validation milestones such as bring-up readiness, stability checkpoints, system integration readiness and production qualification.
Manage risks proactively, drive mitigation strategies, and provide decision-makers with clear options backed by data.
Develop dashboards and reporting mechanisms that provide visibility into validation progress, coverage, blockers, and bug trends.
Minimum Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline.
5+ years of experience in post-silicon validation, hardware engineering program management, or technical program management supporting silicon-based products.
Strong understanding of SoC architecture, high-speed interfaces, memory subsystems, power/thermal domains, and embedded firmware/software interactions.
Demonstrated ability to drive complex, multi-team hardware programs to completion.
Experience working with validation labs, test automation environments, hardware debug workflows, and silicon bring-up.
Excellent communication, organizational, and leadership skills.
Ability to operate independently in ambiguity and influence without authority.
Proven communicator and teammate with experience working effectively with teams across multiple locations.
Experience managing vendors in high-volume silicon-related builds from concept to delivery.
Preferred Qualifications
Experience with custom silicon programs in hyperscale, mobile, XR, or AI/ML accelerator environments.
Familiarity with consumer product development phases (Proto, EVT, DVT, PVT) and hardware quality gates.
Experience with firmware bring-up, bootloaders, security configuration, or low-level driver development.
Experience in system-level validation for products involving sensors, displays or ML workloads.
Proven ability to drive cross-functional debug in complex HW/SW systems.
Results-oriented, proactive, with demonstrated critical thinking and problem-solving skills.
Experience collaborating and/or leading in a team environment.
Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation.
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